1) Field of the Invention
This invention relates to a memory controller for a computer.
2) Description of the Related Art
In the field of computer memory controllers, the following techniques are known inner alia for increasing the effective access speed to a main internal memory:
(1) To use the memory in the form of memory banks upon accessing the memory from a bus master, that is, to interleave memories so that the memories so interleaved can be used as sub-systems.
(2) In the interleaving referred to above, to use as an address to be outputted to one of the memory banks an expected address, which has been obtained by adding "1" to a preceding address of another memory bank, and then to output the predicted address from the preceding cycle.
The interleaving technique will now be described.
FIGS. 1(a) and 1(b) are diagrams showing the interleaved construction of main internal memories.
FIG. 1(a) diagrammatically illustrates the construction of one of the main internal memories, that is, the main internal memory A. Addresses are consecutively allocated to the main internal memory A, ranging from an address 0 to an address m-1. FIG. 1(b), on the other hand, diagrammatically depicts the construction of the other main internal memory, that is, the main internal memory B, which is divided into plural physical units (hereinafter called "banks"). In FIG. 1(b), the main internal memory B is divided by way of example into four banks ranging from a bank 1 to a bank 4. Address 0, address 4, . . . , and address m-4 are allocated to the bank 1, address 1, address 5, . . . , and address m-3 to the bank 2, address 2, address 6, . . . , and address m-2 to the bank 3, and address 3, address 7, . . . , and address m-1 to the bank 4. If the total capacity of the main internal memories A,B is assumed to be m, m is a multiple of 4.
To drive the main internal memory B by a CPU, a desired bank is designated by the least significant two bits of 16-bit address information from the CPU and a desired address in the bank is designated by the most significant 14 bits. Simultaneous feeding of these 14-bit addresses to address registers of the respective banks makes it possible to operate all the banks in parallel. The contents of consecutive addresses can therefore be accessed in a single memory cycle time, whereby a 4-fold speed can be obtained.
A program generally contains more consecutively executed instructions than branch instructions. Interleaving becomes effective when such consecutive areas are accessed.
FIG. 2 is an address state diagram, whereas FIG. 3 is a memory access state diagram. In the address state shown in FIG. 2, two kinds of information, one being instructions and the other data, are used as information to be stored in the memory and the information on the instructions is stored by interleaving. In an instruction memory a, contents a.sub.m are stored at an address m and contents a.sub.m+2 are then stored at an address m+2. In an instruction memory b, contents a.sub.m+1 are stored at an address m+1 and contents a.sub.m+3 are then stored at an address m+3. In a data memory D, on the other hand, contents D.sub.n are stored at an address n and contents D.sub.n+1 are then stored at an address n+1.
In the memory described above, interleaving is performed using the instruction memory a and the instruction memory b. Effects of interleaving are exhibited where data are not accessed and instructions are consecutively accessed.
Now assume that, in FIG. 3, the addresses m to m+4 are those to be used to access instructions while the address n is an address to be used upon accessing data. The instructions corresponding to the addresses m to m+4 are stored in an interleaved fashion in the memory a or memory b, while the data corresponding to the address n are stored in the data memory D.
Where the addresses for accessing the instructions consecutively continue from m to m+2, the address in for accessing the data occurs next, and addresses for accessing instructions again begin from m+3, the address n is located between the address m+2 and the address m+3 so that the continuity of the addresses for accessing the instructions is interrupted and the effects of interleaving are therefore impaired.
FIG. 4 is a time chart illustrating the interleaving.
In the case of a microprocessor in which signal lines are commonly used as address signal lines for instructions and also as address signal lines for data, the above-described construction and operation result in the existence of the data accessing cycle between the instruction accessing cycles as shown in FIG. 4. As a consequence, the continuity of address signals is prevented, leading to the problem that the effects of interleaving are significantly impaired.